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add stm32mp157

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zibright
2025-06-25 16:57:23 +08:00
parent 5e9d7fa54d
commit 65506312ea
2923 changed files with 4174341 additions and 1 deletions
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171
STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/kernel/stm32mp157a-cortex-m4 8-1-mx.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include "stm32mp15-m4-srm.dtsi"
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
model = "STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06";
compatible = "st,stm32mp157a-cortex-m4 8-1-mx", "st,stm32mp157";
/* !!! log : Warning - no DDR config found: 'memory' node not generated !!! */
/*
memory@??? {
reg = < ??? >;
};
*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* USER CODE BEGIN reserved-memory */
/* USER CODE END reserved-memory */
};
/* USER CODE BEGIN root */
/* USER CODE END root */
clocks{
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
};
}; /*root*/
&pinctrl {
m4_i2c1_pins_mx: m4_i2c1_mx-0 {
pins {
pinmux = <STM32_PINMUX('F', 14, RSVD)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
};
};
/* USER CODE BEGIN pinctrl */
/* USER CODE END pinctrl */
};
&pinctrl_z {
/* USER CODE BEGIN pinctrl_z */
/* USER CODE END pinctrl_z */
};
&m4_rproc{
status = "okay";
/* USER CODE BEGIN m4_rproc */
/* USER CODE END m4_rproc */
m4_system_resources{
status = "okay";
/* USER CODE BEGIN m4_system_resources */
/* USER CODE END m4_system_resources */
};
};
&bsec {
status = "okay";
/* USER CODE BEGIN bsec */
/* USER CODE END bsec */
};
&dma1 {
status = "okay";
/* USER CODE BEGIN dma1 */
/* USER CODE END dma1 */
};
&dma2 {
status = "disabled";
/* USER CODE BEGIN dma2 */
/* USER CODE END dma2 */
};
&dmamux1 {
status = "okay";
dma-masters = <&dma1>;
dma-channels = <8>;
/* USER CODE BEGIN dmamux1 */
/* USER CODE END dmamux1 */
};
&m4_dma2 {
status = "okay";
/* USER CODE BEGIN m4_dma2 */
/* USER CODE END m4_dma2 */
};
&m4_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&m4_i2c1_pins_mx>;
status = "okay";
/* USER CODE BEGIN m4_i2c1 */
/* USER CODE END m4_i2c1 */
};
&m4_timers3 {
status = "okay";
/* USER CODE BEGIN m4_timers3 */
/* USER CODE END m4_timers3 */
};
&mdma1 {
status = "okay";
/* USER CODE BEGIN mdma1 */
/* USER CODE END mdma1 */
};
&rcc {
status = "okay";
/* USER CODE BEGIN rcc */
/* USER CODE END rcc */
};
&rtc {
status = "okay";
/* USER CODE BEGIN rtc */
/* USER CODE END rtc */
};
&tamp {
status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
/* USER CODE BEGIN addons */
/* USER CODE END addons */

171
STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/optee-os/stm32mp157a-cortex-m4 8-1-mx.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <dt-bindings/soc/stm32mp15-etzpc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
model = "STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06";
compatible = "st,stm32mp157a-cortex-m4 8-1-mx", "st,stm32mp157";
/* !!! log : Warning - no DDR config found: 'memory' node not generated !!! */
/*
memory@??? {
reg = < ??? >;
};
*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* USER CODE BEGIN reserved-memory */
/* USER CODE END reserved-memory */
};
/* USER CODE BEGIN root */
/* USER CODE END root */
clocks {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
clk_hsi: clk-hsi {
clock-frequency = <64000000>;
/* USER CODE BEGIN clk_hsi */
/* USER CODE END clk_hsi */
};
clk_lse: clk-lse {
status = "disabled";
/* USER CODE BEGIN clk_lse */
/* USER CODE END clk_lse */
};
clk_hse: clk-hse {
status = "disabled";
/* USER CODE BEGIN clk_hse */
/* USER CODE END clk_hse */
};
};
}; /*root*/
/*Warning: the configuration of the secured GPIOs should be added in (addons) User Section*/
&pinctrl {
/* USER CODE BEGIN pinctrl */
/* USER CODE END pinctrl */
};
&pinctrl_z {
/* USER CODE BEGIN pinctrl_z */
/* USER CODE END pinctrl_z */
};
&bsec {
status = "okay";
/* USER CODE BEGIN bsec */
/* USER CODE END bsec */
};
&etzpc {
status = "okay";
st,decprot = <
/*"Non Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*"Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
/*"Mcu Isolation" peripherals*/
DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM3_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_SRAMx_ID STM32MP1_ETZPC_RETRAM_ID STM32MP1_ETZPC_BKPSRAM_ID*/
/* USER CODE BEGIN etzpc_decprot */
/*STM32CubeMX generates a basic and standard configuration for ETZPC.
Additional device configurations can be added here if needed.
"etzpc" node could be also overloaded in "addons" User-Section.*/
/* USER CODE END etzpc_decprot */
>;
/* USER CODE BEGIN etzpc */
/* USER CODE END etzpc */
};
&rcc {
status = "okay";
/* USER CODE BEGIN rcc */
/* USER CODE END rcc */
st,clksrc = <
CLK_CKPER_DISABLED
CLK_STGEN_HSI
CLK_I2C12_PCLK1
CLK_MPU_HSI
CLK_AXI_HSI
CLK_MCU_HSI
CLK_RTC_LSI
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 0)
DIV(DIV_APB2, 0)
DIV(DIV_APB3, 0)
DIV(DIV_APB4, 0)
DIV(DIV_APB5, 0)
DIV(DIV_RTC, 0)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
/* USER CODE BEGIN rcc_st-pll_vco */
/* USER CODE END rcc_st-pll_vco */
};
};
&rtc {
status = "okay";
/* USER CODE BEGIN rtc */
/* USER CODE END rtc */
};
&tamp {
status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
/* USER CODE BEGIN addons */
/* USER CODE END addons */

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STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/tf-a/stm32mp15-mx.dtsi Normal file
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/*
* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0-or-later BSD-3-Clause
*
*/
/*
* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
*/
/*
*
* Device tree generated from STM32CubeMX project without DDR IP correctly configured.
* If you need the DDR configuration to be part of your device tree, ensure you have proper
* DDR ip configuration in your STM32CubeMX project and generate device tree.
*
*/

12
STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/tf-a/stm32mp157a-cortex-m4 8-1-mx-fw-config.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/* !!! log : Warning - DDR not configured: FW config not generated !!! */
/*#include "???-fw-config.dts"*/

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STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/tf-a/stm32mp157a-cortex-m4 8-1-mx.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
/* !!! log : Warning - DDR not configured: unknown DDR dtsi !!! */
/*#include "???-ddr.dtsi"*/
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
model = "STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06";
compatible = "st,stm32mp157a-cortex-m4 8-1-mx", "st,stm32mp157";
/* !!! log : Warning - no DDR config found: 'memory' node not generated !!! */
/*
memory@??? {
reg = < ??? >;
};
*/
/* USER CODE BEGIN root */
/* USER CODE END root */
clocks {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
clk_hsi: clk-hsi {
clock-frequency = <64000000>;
/* USER CODE BEGIN clk_hsi */
/* USER CODE END clk_hsi */
};
clk_lse: clk-lse {
status = "disabled";
/* USER CODE BEGIN clk_lse */
/* USER CODE END clk_lse */
};
clk_hse: clk-hse {
status = "disabled";
/* USER CODE BEGIN clk_hse */
/* USER CODE END clk_hse */
};
};
}; /*root*/
&pinctrl {
/* USER CODE BEGIN pinctrl */
/* USER CODE END pinctrl */
};
&pinctrl_z {
/* USER CODE BEGIN pinctrl_z */
/* USER CODE END pinctrl_z */
};
&rcc {
status = "okay";
/* USER CODE BEGIN rcc */
/* USER CODE END rcc */
st,clksrc = <
CLK_CKPER_DISABLED
CLK_STGEN_HSI
CLK_MPU_PLL1P
CLK_AXI_HSI
CLK_MCU_HSI
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 0)
DIV(DIV_APB2, 0)
DIV(DIV_APB3, 0)
DIV(DIV_APB4, 0)
DIV(DIV_APB5, 0)
DIV(DIV_RTC, 0)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
/* USER CODE BEGIN rcc_st-pll_vco */
/* USER CODE END rcc_st-pll_vco */
};
};
/* USER CODE BEGIN addons */
/* USER CODE END addons */

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STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/u-boot/stm32mp157a-cortex-m4 8-1-mx-u-boot.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
/* USER CODE BEGIN root */
/* USER CODE END root */
}; /*root*/
/* USER CODE BEGIN addons */
/* USER CODE END addons */

171
STM32MP157AAA3/Cortex-M4 8-1/CA7/DeviceTree/Cortex-M4 8-1/u-boot/stm32mp157a-cortex-m4 8-1-mx.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157.dtsi"
#include "stm32mp15xa.dtsi"
#include "stm32mp15xxaa-pinctrl.dtsi"
#include "stm32mp15-m4-srm.dtsi"
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
model = "STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06";
compatible = "st,stm32mp157a-cortex-m4 8-1-mx", "st,stm32mp157";
/* !!! log : Warning - no DDR config found: 'memory' node not generated !!! */
/*
memory@??? {
reg = < ??? >;
};
*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* USER CODE BEGIN reserved-memory */
/* USER CODE END reserved-memory */
};
/* USER CODE BEGIN root */
/* USER CODE END root */
clocks{
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
};
}; /*root*/
&pinctrl {
m4_i2c1_pins_mx: m4_i2c1_mx-0 {
pins {
pinmux = <STM32_PINMUX('F', 14, RSVD)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
};
};
/* USER CODE BEGIN pinctrl */
/* USER CODE END pinctrl */
};
&pinctrl_z {
/* USER CODE BEGIN pinctrl_z */
/* USER CODE END pinctrl_z */
};
&m4_rproc{
status = "okay";
/* USER CODE BEGIN m4_rproc */
/* USER CODE END m4_rproc */
m4_system_resources{
status = "okay";
/* USER CODE BEGIN m4_system_resources */
/* USER CODE END m4_system_resources */
};
};
&bsec {
status = "okay";
/* USER CODE BEGIN bsec */
/* USER CODE END bsec */
};
&dma1 {
status = "okay";
/* USER CODE BEGIN dma1 */
/* USER CODE END dma1 */
};
&dma2 {
status = "disabled";
/* USER CODE BEGIN dma2 */
/* USER CODE END dma2 */
};
&dmamux1 {
status = "okay";
dma-masters = <&dma1>;
dma-channels = <8>;
/* USER CODE BEGIN dmamux1 */
/* USER CODE END dmamux1 */
};
&m4_dma2 {
status = "okay";
/* USER CODE BEGIN m4_dma2 */
/* USER CODE END m4_dma2 */
};
&m4_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&m4_i2c1_pins_mx>;
status = "okay";
/* USER CODE BEGIN m4_i2c1 */
/* USER CODE END m4_i2c1 */
};
&m4_timers3 {
status = "okay";
/* USER CODE BEGIN m4_timers3 */
/* USER CODE END m4_timers3 */
};
&mdma1 {
status = "okay";
/* USER CODE BEGIN mdma1 */
/* USER CODE END mdma1 */
};
&rcc {
status = "okay";
/* USER CODE BEGIN rcc */
/* USER CODE END rcc */
};
&rtc {
status = "okay";
/* USER CODE BEGIN rtc */
/* USER CODE END rtc */
};
&tamp {
status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
/* USER CODE BEGIN addons */
/* USER CODE END addons */